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| products and specifications discussed herein ar e subject to change by micron without notice. 2, 4, and 8gb x8/x16 multiplexed nand flash memory features 09005aef818a56a7 pdf/09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__1.fm - rev. c 5/05 en 1 ?2004 micron technology, inc. all rights reserved. nand flash memory mt29f2g08aabwp/mt29f2g16aabwp mt29f4g08babwp/mt29f4g16babwp mt29f8g08fabwp features ? organization: page size: x8: 2,112 bytes (2,048 + 64 bytes) x16: 1,056 words (1,024 + 32 words) block size: 64 pages (128k + 4k bytes) device size: 2gb: 2,048 blocks; 4gb: 4,096 blocks; 8gb: 8,192 blocks read performance: random read: 25s sequential read: 30ns (3v x8 only) write performance: page program: 300s (typ) block erase: 2ms (typ) endurance: progra m/erase cycles (with ecc and invalid block mapping) first block (block address 00h) guaranteed to be valid without ecc (up to 1,000 program/erase cycles) v cc : 2.7v?3.6v automated program and erase basic nand command set: page read, random data read, read id, read status, program page, random data input, program page cache mode, internal data move, internal data move with random data input, block erase, reset new commands: page read cache mode read unique id (contact factory) read id2 (contact factory) operation status byte provides a software method of detecting: program/erase operation completion program/erase pass/fail condition write-protect status ready/busy# (r/b#) pin provides a hardware method of detecting program or erase cycle completion pre pin: prefetch on power up wp# pin: hardware write protect figure 1: 48-pin tsop type 1 options marking density: 2gb (single die) mt29f 2g xxaab 4gb (dual-die stack) mt29f 4g xxbab 8gb (quad-die stack) mt29f 8g xxfab device width: x8 mt29fxx 08 x x16 mt29fxx 16 x configuration: # of die # of ce# # of r/b# 11 1 a 21 1 b 42 2 f v cc : 2.7v?3.6v a second generation die b package: 48 tsop type i (lead-free plating) wp 48 tsop type i (contact factory) wg operating temperature: commercial (0?70c) ? extended temperature (-40c to +85c) et
09005aef818a56a7 pdf/09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__1.fm - rev. c 5/05 en 2 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory part numbering information part numbering information micron nand flash devices ar e available in several different configurations and densi- ties. (see figure 2.) figure 2: part number chart valid part number combinations after building the part number from the part numbering chart above, verify that the part number is valid using the micron part marking decoder web site at http://www.micron.com/partsearch to verify that the part number is offered and valid. if the device required is not on this list, contact the factory. mt 29f 2g 08 a a b wp es micron technology product family 29f = single-supply nand flash memory density 2g = 2gb 4g = 4gb 8g = 8gb device width 08 = 8 bits 16 = 16 bits operating voltage range a = 3.3v (2.70v?3.60v) production status blank = production es = engineering sample ms = mechanical sample operating temperature range blank = commercial (0c to +70c) et = extended (-40 to +85c) reserved for future use reserved for future use package codes wp = 48-pin tsop i (lead-free) wg = 48-pin tsop i (contact factory) generation a = 1st generation die b = 2nd generation die c = 3rd generation die classification # of die # of ce# # of r/b# i/o a 1 1 1 common b 2 1 1 common f 4 2 2 common 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29btoc.fm - rev. c 5/05 en 3 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 part numbering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 ready/busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 minimum rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 power-on auto-read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 command definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 page read 00h?30h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 random data read 05h?e0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 page read cache mode start 31h; page read cache mo de start last 3fh . . . . . . . . . . . . . . . . .24 read id 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 read status 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 program page 80h?10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 serial data input 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 random data input 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 program page cache mode 80h?15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 read for internal data move 00h?35h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 internal data move 85h?10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 block erase 60h?d0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 reset ffh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 write protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 error management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 v cc power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2, 4, and 8gb x8/x16 multiplexed nand flash memory list of figures 09005aef818a56a7 pdf/ 09005aef81590bdd zip micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29blof.fm - rev. c 5/05 en 4 ?2004 micron technology, inc. all rights reserved. list of figures figure 1: 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 3: nand flash functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: pin assignment (top view) 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 5: memory map x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: memory map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 7: array organization for mt29f2g08axb (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 8: array organization for mt29f2g16axb (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 9: array organization for mt29f4g08bxb and mt29f8g08f xb (x8) . . . . . . . . . . . . . . . . . . . . . . . .13 figure 10: array organization for mt29f4g16bxb (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 11: ready/busy# open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 12: tr and tf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: iol vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 14: tc vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: first page power-on auto-read (3v v cc only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 16: ac waveforms during power transi tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 17: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 18: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 19: page read cache mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 20: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 21: status register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 22: program and read status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 23: random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 24: program page cache mo de example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 25: internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 26: internal data move with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 27: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 28: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 29: erase enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 30: erase disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 31: program enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 32: program disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 33: command latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 34: address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 35: input data latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 36: serial access cycle after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 37: status read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 38: page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 39: read operation with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 40: random data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 41: page read cache mode timing diagram, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 42: page read cache mode timing diagram, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 43: page read cache mode timing wi thout r/b#, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 44: page read cache mode timing wi thout r/b#, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 45: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 46: program operation with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 47: program page operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 48: program page operat ion with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 49: internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 50: program page cache mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 51: program page cache mo de ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4 figure 52: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 53: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 54: package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2, 4, and 8gb x8/x16 multiplexed nand flash memory list of tables 09005aef818a56a7 pdf/ 09005aef81590bdd zip micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29blot.fm - rev. c 5/05 en 5 ?2004 micron technology, inc. all rights reserved. list of tables table 1: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 2: array addressing: mt29f2g08axb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 3: array addressing: mt29f2g16axb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 4: array addressing: mt29f4g08bxb and mt29f8g08fxb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 5: array addressing: mt29f4g16bxb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 7: command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 8: device id and configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 9: status register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 10: status register contents after re set operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 11: absolute maximum ratings by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 12: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 13: dc and operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 14: valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 15: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 16: test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 17: ac characteristics?command, data, and address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 18: ac characteristics?normal operatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 19: program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 6 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory general description general description nand technology provides a cost-effective solution for applications requiring high- density solid-state storage. the mt29f 2g08axb and mt29f2g16axb are 2gb nand flash memory devices. the mt29f4g08bxb and mt29f4g16bxb are two-die stacks that operate as a single 4gb device. the mt29f8g08f ab is a four-die stac k that operates as two independent 4gb devices (mt29f4g08bxb) , providing a total storage capacity of 8gb in a single, space-saving package. micron ? nand flash devices include standard nand features as well as new features de signed to enhance system-level performance. micron nand flash devices use a highly mu ltiplexed 8- or 16-b it bus (i/o[7:0] or i/o[15:0]) to transfer data, addresses, and instructions. the five command pins (cle, ale, ce#, re#, we#) implement the nand command bus interface protocol. three additional pins control hardware write protec tion (wp#), monitor device status (r/b#), and initiate the auto-read feature (pre?3v device only). note that the pre function is not supported on extended-temperature devices. this hardware interface creates a low-pin-coun t device with a standard pinout that is the same from one density to another, allowing future upgrades to higher densities with- out board redesign. mt29f2g and mt29f4g devices contain 2,048 and 4,096 erasable blocks respectively. each block is subdivided into 64 programmabl e pages. each page consists of 2,112 bytes (x8) or 1,056 words (x16). the pages are further divided into a 2,048-byte data storage region with a separate 64-byte area on the x8 device; and on the x16 device, separate 1,024-word and 32-word areas. the 64-byte and 32-word areas are typically used for error management functions. the contents of each 2,112-byte page can be programmed in 300s, and an entire 132k- byte/66k word block can be erased in 2ms. on-chip control logic automates program and erase operations to maximize cycle endurance. erase/program endurance is specified at 100,000 cycles when using appr opriate error correcting code (ecc) and error management. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 7 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory general description figure 3: nand flash functional block diagram note: the pre function is not suppo rted on extended-temperature devices. figure 4: pin assignment (top view) 48-pin tsop type 1 notes: 1. ce2# and r/b2# on 8gb device only. th ese pins are nc for other configurations. 2. the pre function is not supported on extended-temperature devices. address register data register cache register status register command register ce# v cc v ss cle ale we# re# wp# (3v i/o only) pre i/o [7:0] i/o [15:0] control logic i/o control r/b# row decode column decode x8 nc nc nc nc nc r/b2# 1 r/b# re# ce# ce2# 1 nc vcc vss nc nc cle ale we# wp# dnu dnu dnu nc nc x16 nc nc nc nc nc nc r/b# re# ce# nc nc vcc vss nc nc cle ale we# wp# dnu dnu dnu nc nc x16 vss i/o15 i/o7 i/o1 4 i/o6 i/o13 i/o5 i/o12 i/o4 nc pre 2 vcc nc nc nc i/o11 i/o3 i/o1 0 i/o2 i/o9 i/o1 i/o8 i/o0 vss x8 nc nc nc nc i/o7 i/o6 i/o5 i/o4 nc nc pre 2 vcc vss nc nc nc i/o3 i/o2 i/o1 i/o0 nc nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 8 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory general description notes: 1. the pre function is not suppo rted on extended-temperature devices. table 1: pin descriptions symbol type pin function ale input address latch enable: duri ng the time ale is high, address information is transferred from i/o[7:0] into the on-c hip address register upon a low to high transition on we# . when address information is not being loaded, the ale pin should be driven low. ce#, ce2# input chip enable: gates transfers between the host system and the nand device. once the device starts a program or erase operat ion, the chip enab le pin can be de- asserted. for the 8gb configuration, ce# controls the first 4gb of memory; ce2# controls the second 4gb. s ee the bus operation section, starting on page 15, for additional operational details. cle input command latch enable: when cle is hi gh, information is transferred from i/o[7:0] to the on-chip co mmand register on the rising edge of we#. when command information is not being loaded, the cle pin should be driven low. pre 1 (3v device only) input power-on read enable: enab les the auto-read fu nction when at vcc. see the bus operation section, starting on page 15, for additional details. re# input read enable: gates transfers from th e nand device to the host system. we# input write enable: gates transfers from the host system to the nand device. wp# input write protect: pin protects against inad vertent program and erase operations. all program and erase operations are disabled when the wp# pin is low. i/o[7:0] mt29fxg08 i/o[15:0] mt29fxg16 i/o data inputs/outputs: the bidirectional i/o pins transfer address, data, and instruction information. data is output only during read operations; at other times the i/o pins are inputs. r/b#, r/b2# output ready/busy: an open-drain, active-low output, that uses an external pull-up resistor. the pin is used to indicate wh en the chip is processing a program or erase operation. the pin is also used du ring a read operation to indicate when data is being transferred from the array in to the serial data register. once these operations have completed, the r/b# retu rns to the high-impedance state. in the 8gb configuration, r/b# is for the 4gb of memory enabled by ce#; r/b2# is for the 4gb of memory enabled by ce2#. v cc supply v cc : the v cc pin is the power supply pin. v ss supply v ss : the v ss pin is the ground connection. nc ? no connect: nc pins are not internally connected. these pins can be driven or left unconnected. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 9 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory architecture architecture these devices use nand electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins. this provides a memory device with a low pin count. the internal memory array is accessed on a pa ge basis. when doing reads, a page of data is copied from the memory array into the data register. once copied to the data register, data is output sequentially, byte by byte on x8 devices, or word by word on x16 devices. the memory array is programmed on a page basis. after the starting address is loaded into the internal address register, data is sequ entially written to the internal data register up to the end of a page. after all of the page data has been loaded into the data register, array programming is started. in order to increase programming bandwidth, this device incorporates a cache register. in the cache programming mode, data is first copied into the cache register and then into the data register. once the data is copied into the data register, programming begins. after the data register has been loaded an d programming started, the cache register becomes available for loading additional data. loading the next page of data into the cache register takes place while page programming is in process. the internal data move command also uses the internal cache register. normally, moving data from one area of external memo ry to another uses a large number of exter- nal memory cycles. by using the internal cach e register and data register, array data can be copied from one page and then progra mmed into another without using external memory cycles. addressing nand flash devices do not contain dedicate d address pins. addresses are loaded using a five-cycle sequence as shown in figures 7 and 8, on pages 11 and 12 respectively. table 2 on page 11 presents address function s internal to the x8 device; table 3 on page 12 covers the same functions for the x16 device. see figures 5 and 6 on page 10 for additional memory mappin g and addressing details. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 10 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory addressing figure 5: memory map x8 figure 6: memory map x16 note: block address and page address = actual page address. a11 a17 a12 a28 (4gb: a29) a18 a11 a0 a0 a5 page 63-0 column address within a page page address within a block block address 000bf83fh 00080000h 0007f83fh 00040000h 0003f83fh 0 1ffff83fh 1ffc0000h (4gb: 3ffff83fh) (4gb: 3ffc0000h) spare address within a page a10 a16 a11 a 27 (4gb: a28) a17 a10 a0 a0 a4 page 63-0 column address page address within a block block address 005f41fh 0040000h 003f41fh 0020000h 001f41fh 0 ffff41fh ffe0000h spare address within a page (4gb: 1ffffc1fh) (4gb: 1ffe0000h) 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 11 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory addressing figure 7: array organization for mt29f2g08axb (x8) note: cax = column addr ess; rax = row address. table 2: array addressing: mt29f2g08axb cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low ca11 ca10 ca9 ca8 third ra19 ra18 ra17 ra16 ra15 ra14 ra13 ra12 fourth ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 fifth low low low low low low low ra28 cache register data register 2,048 blocks per device 1 block 64 2,048 64 2,048 2,112 bytes i/o 7 i/o 0 64 pages = 1 block (128k + 4k) bytes 1 page = (2k + 64 bytes) 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 device = (2k + 64) bytes x 64 pages x 2,048 blocks = 2,112 mb 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 12 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory addressing figure 8: array organization for mt29f2g16axb (x16) notes: 1. cax = column addr ess; rax = row address. 2. i/o[15:8] are not used during the addre ssing sequence and should be driven low. table 3: array addressing: mt29f2g16axb cycle i/o[15:8] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low low low ca10 ca9 ca8 third low ra18 ra17 ra16 ra15 ra14 ra13 ra12 ra11 fourth low ra26 ra25 ra24 ra23 ra22 ra21 ra20 ra19 fifth low low low low lo wlowlowlowra27 cache register data register 2,048 blocks per device 1 block 32 1,024 32 1,024 1,056 words i/o 15 i/o 0 64 pages = 1 block (64k + 2k) words 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 device = (1k + 32) words x 64 pages x 2,048 blocks = 2,112 mb 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 13 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory addressing figure 9: array organization for mt29f4g08bxb and mt29f8g08fxb (x8) note: for the 8gb mt29f8g08f, the 4gb array or ganization shown here applies to each chip enable (ce# and ce2#). notes: 1. die address boundary: 0 = 0 ? 2gb, 1 = 2gb ? 4gb. table 4: array addressing: mt29f4g08bxb and mt29f8g08fxb cax = column address; rax = row address. cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7ca6ca5ca4ca3ca2ca1ca0 second low low low low ca11 ca10 ca9 ca8 third ra19 ra18 ra17 ra16 ra15 ra14 ra13 ra12 fourth ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 fifth low low low low low low ra29 1 ra28 cache register data register 4,096 blocks 1 block 64 2,048 64 2,048 2,112 bytes i/o 7 i/o 0 64 pages = 1 block (128k + 4k) bytes 1 page = (2k + 64 bytes) 1 block = (2k + 64) bytes x 64 pages = (128k + 4k) bytes 1 device = (2k + 64) bytes x 64 pages x 4,096 blocks = 4,224 mb 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 14 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory addressing figure 10: array organization for mt29f4g16bxb (x16) notes: 1. die address boundary: 0 = 0 ? 2gb, 1 = 2gb ? 4gb. 2. i/o[15:8] are not used during the addre ssing sequence and should be driven low. table 5: array addressing: mt29f4g16bxb cax = column address; rax = row address. cycle i/o[15:8] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first low ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low low low low ca10 ca9 ca8 third low ra18ra17ra16ra15ra14ra13ra12ra11 fourth low ra26ra25ra24ra23ra22ra21ra20ra19 fifth low low low low low low low ra28 1 ra27 cache register data register 4,096 blocks per device 1 block 32 1,024 32 1,024 1,056 words i/o 15 i/o 0 64 pages = 1 block (64k + 2k) words 1 page = (1k + 32) words 1 block = (1k + 32) words x 64 pages = (64k + 2k) words 1 device = (1k + 32) words x 64 pages x 4,096 blocks = 4,224 mb 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 15 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory bus operation bus operation the bus on the mt29fxxx devices is multip lexed. data i/o, addresses, and commands all share the same pins. i/o pins i/o[15:8] ar e used only for data in the x16 configura- tion. addresses and commands are always supplied on i/o[7:0]. the command sequence normally consists of a command latch cycle, an address latch cycle, and a data cycle?either read or write. control signals ce#, we#, re#, cle, ale and wp# control flash device read and write operations. on the 8gb mt29f8g08fab, ce# and ce2# each control independent 4gb arrays. ce2# functions the same as ce# for its own array; all operations described for ce# also apply to ce2#. ce# is used to enable the device. when ce# is low and the device is not in the busy state, the flash memory will accept command, data, and address information. when the device is not performing an operat ion, the ce# pin is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power con- sumption. see figure 39 on page 46 and figure 46 on page 51 for examples of ce# ?don?t care? operations. the ce# ?don?t care? operation allows the nand flash to reside on the same asynchro- nous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flash is busy with internal operations. this capa- bility is important for designs that require multiple nand devices on the same bus. one device can be programmed while another is being read. a high cle signal indicates th at a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. commands commands are written to the command register on the rising edge of we# when: ce# and ale are low, and cle is high, and the device is not busy. the exceptions to this are the read status and reset commands. commands are transferred to the command register on the rising edge of we#. see figure 33 on page 43. commands are input on i/o[7:0] only. for devices with a x16 interface, i/o[15:8] must be written with zeros when issuing a command. address input addresses are written to the address register on the rising edge of we# when: ce# and cle are low, and ale is high, and the device is not busy. addresses are input on i/o[7:0] only. for devi ces with a x16 interface, i/o[15:8] must be written with zeros when issuing an address. generally all five address cycles are written to the device. an exception to this is the block erase command, which requires only three address cycles. see the ?block erase operation? section on page 33 for details. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 16 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory bus operation random data input and output commands need only column addresses, so only two address cycles are required. refer to the command descriptions to determine the addressing requirements for each command. data input data is written to the data register on the rising edge of we# when: ce#, cle, and ale are low, and the device is not busy. data is input on i/o[7:0] for x8 devices, and i/o[15:0] on x16 devices. see figure 35 on page 44 for additional data input details. reads after a read command is sent to the memory device, data is transferred from the mem- ory array to the data register in t r from the rising edge of we#, and r/b# goes low. typ- ically t r is 25s. r/b# returns to high at this time. once data is available in the data register, it is clocked out of the part by re# going low. see figure 38 on page 45 for detailed timing information. the read status (70h) command or the r/b# signal can be used to determine when the device is ready. see the status read command section on page 28 for details. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 17 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory bus operation ready/busy# the r/b# output provides a hardware method of indicating the completion of a pro- gram/erase/read operation. the signal is typically high, and transitions to low after the appropriate command is written to the device. the signal pin?s open-drain driver enables multiple r/b# outputs to be or-tied. the signal requires a pull-up resis- tor for proper operation. the read status command can be used in place of r/b#. typically r/b# would be connected to an in terrupt pin on the system controller. see figure 11 on page 18 . on the 8gb mt29f8g08fab, r/b# provides an indication for the 4gb section enabled by ce#, and r/b2# does the same for the 4gb section enabled by ce2#. r/b# and r/b2# can be tied together, or they can be used sepa rately to provide inde pendent indications for each 4gb section. the combination of rp and capacitive loadin g of the r/b# circuit determines the rise time of the r/b# pin. the actual value used for rp depends on the system timing requirements. large values of rp cause r/b# to be delayed significantly. at the 10- to 90- percent points on the r/b# waveform, rise time is approximately two time constants (tc). tc = rc where r = rp and c = total capacitive load the fall time of the r/b# signal is determ ined mainly by the output impedance of the r/b# pin and the total load capacitance. refer to figure 12 on page 18, and figure 13 on page 19 , which depict approximate rp values using a circuit load of 100pf. the minimum value for rp is determined by th e output drive capability of the r/b# sig- nal, the output voltage swing, and v cc . minimum rp where i l is the sum of the input currents of all devices tied to the r/b# p in. rp (min, 3.3v part) = v cc (max) ? v ol (max) i ol + i l = 3.2v 8ma + i l 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 18 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory bus operation figure 11: ready/busy# open drain figure 12: t r and t f notes: 1. t r and t f calculated at 10%?90% points. 2. t r dependent on external capacitance and resistive load ing and output transistor impedance. 3. t r primarily dependent on external pull-up resistor and external capacitive loading. 4. t f 10ns @ 3.3v. 5. see tc values in figure 14 on page 19 for approximate rp value and tc. rp r/b# open drain outpu t v cc gnd device i ol 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 6 t f t r tc v 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 19 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory bus operation figure 13: i ol vs. rp figure 14: tc vs. rp 3.50ma 3.00ma 2.50ma 2.00ma 1.50ma 1.00ma 0.50ma 0.00ma 0 2000 4000 6000 8000 10000 12000 i ol @3.60v (max) rp i 1.20 s 1.00 s 800ns 600ns 400ns 200ns 0ns 0 2k ? 4k ? 6k ? 8k ? 10k ? 12k ? i ol @3.60v (max) rc = tc c = 100pf rp t 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 20 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory bus operation notes: 1. wp# should be biased to cmos high or low for standby. 2. pre should be tied to v cc or ground. do not transition pre during device operations. the pre function is not supported on extended-temperature devices. 3. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . table 6: mode selection cle ale ce# we# re# wp# 1 pre 2 mode hll hx x read mode command input lhl hx x address input hll hh x write mode command input lhl hh x address input lll hh x data input lllh x x sequential read and data output lllhhx x during read (busy) xxxxxh x during program (busy) xxxxxh x during erase (busy) xxxxxl x write protect x x h x x 0v/vcc 0v/vcc standby 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 21 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory bus operation power-on auto-read during power-on, with the pre pin at v cc , 3v v cc devices automatically transfer the first page of the memory array to the data register without requiring a command or address-input sequence. as v cc reaches approximately 2.5v, the internal voltage detec- tor initiates the power-on auto-read function. r/b# will stay low ( t rpre) while the first page of data is copied into the data register. see table 18 on page 42 for the t rpre value. once the read is complete and r/b# goes high, re# can be pulsed to output the first page of data. the pre function is not supported on extended-temperature devices. figure 15: first page power-on auto-read (3v v cc only) notes: 1. verified per device characterization; not 100% tested on all devices. 2. the pre function is not supported on extended-temperature devices. figure 16: ac waveforms during power transitions 2.5v 1 vcc cle ce# we# ale pre r/b# re# i/ox t rpre 1st 2nd 3rd n th ..... undefined we# r/b# wp# vcc 10s high 3v device: 2.5v 3v device: 2.5 v undefined don't care 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 22 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions command definitions notes: 1. do not cross die address boundaries when using cache operations. see tables 4 and 5 for definition of die address boundaries. 2. do not cross die address boundaries when using read for internal data move and program for internal data mo ve. see tables 4 and 5 for definition of die address boundaries. 3. random data read command limite d to use within a single page. 4. random data input for program command limited to use within a single page. table 7: command set operation cycle 1 cycle 2 valid during busy page read 00h 30h no page read cache mode start 1 31h ? no page read cache mode start last 1 3fh ? no read for internal data move 2 00h 35h no random data read 3 05h e0h no read id 90h ? no read status 70h ? yes program page 80h 10h no program page cache 1 80h 15h no program for internal data move 2 85h 10h no random data input for program 4 85h ? no block erase 60h d0h no reset ffh ? yes 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 23 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions read operations page read 00h?30h on initial power up, each device defaults to read mode. to enter the read mode while in operation, write the 00h?30h command sequence to the command register along with the five address cycles. writing 00h to the command register starts the address latch cycle. five address cycles are input next. finally the 30h command is loaded into the command register. while monitoring the read status to determine when the t r (transfer from flash array to data register) is complete, the user must re -issue the read (00h) command to make the change from status to data. (see figure 43 on page 49 and figure 44 on page 50 for examples.) after the read command has been re-issued, pulsing the re# line will result in outputting data, starting fr om the initial column address. a serial page read sequence outputs a complete page of data. after 30h is written, the page data is transferred to the data regist er, and r/b# goes low during the transfer. when the transfer to the data register is complete, r/b# returns high. at this point, data can be read from the device. starting from the initial column address to the end of the page, read the data by repeatedly pulsing re# at the maximum t rc rate. (see figure 17 on page 23.) figure 17: page read operation re# ce# ale cle i/ox 00h address (5 cycles) data output (serial access) 30h r/b# we# t r don?t care 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 24 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions random data read 05h?e0h the random data read command enables the user to specify a new column address so the data at single or multiple addresses can be read. the random read mode is enabled after a normal page read (00h?30h sequence). random data can be output after the initial page read by writing an 05h?e0h command sequence along with the new column address (two cycles). the random data read command can be issued without limit within the page. only data on the current page can be read. pulsing the re# pin outputs data sequen- tially. see figure 18 on page 24. figure 18: random data read operation page read cache mode start 31h; page read cache mode start last 3fh micron nand flash devices have a cache register that can be used to increase read operation speed when accessing sequential pages in a block. first, a normal page read (00h?30h) command sequence is issued. (see figure 19 on page 25 for operation details.) the r/b# signal goes low for t r during the time it takes to transfer the first page of data from the memory to the data register. after r/b# returns to high, the page read cache mode st art (31h) command is latched into the command register. r/b# goes low for t dcbsyr1 while data is being transferred from the data register to the cache register. once the data register contents are transferred to the cache register, another page read is au tomatically started as part of the 31h com- mand. data is transferred from the next sequential page of the memory array to the data register during the same time data is being re ad serially (pulsing of re#) from the cache register. if the total time to output data exceeds t r, then the page read is hidden. the second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands. r/b# will stay low up to t dcbsyr2. this time can vary, depending on whether the previous memory -to-data-register transfer was completed prior to issuing the next 31h command. if the data transfer from memory to the data reg- ister is not completed before the 31h comma nd is issued, r/b# stays low until the transfer is complete. it is not necessary to output a whole page of data before issuing another 31h command. r/b# will stay low until the previous page read is complete and the data has been transferred to the cache register. to read out the last page of data, the page read cache mode start last (3fh) command is issued. this command transfers da ta from the data register to the cache register without issuing another page read. (see figure 19 on page 25 .) re# i/ox 00h address (5 cycles) data output data output 30h 05h address (2 cycles) e0h r/b# t r 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 25 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions figure 19: page read cache mode re# ce# ale cle i/ox 00h address (5 cycles) data output (serial access) data output (serial access) 31h 30h 31h 3fh r/b# we# t r data output (serial access) t dcbsyr1 t dcbsyr2 t dcbsyr2 don?t care 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 26 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions read id 90h the read id command is used to read the 4 bytes of identifier codes programmed into the devices. the read id command reads a 4- byte table that includes manufacturer?s id, device configuration, and part-specific information. see table 8 on page 27, which shows complete listings of all configuration details. writing 90h to the command register puts the device into the read id mode. the com- mand register stays in this mode until another valid command is issued. (see figure 20 .) figure 20: read id operation notes: 1. see table 8 on page 27. device id 1 don't care we# ce# ale cle re# i/ox address, 1 cycle 90h 00h manufacturer id 1 byte 2 byte 0 byte 1 byte 3 1 t ar t rea t whr 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 27 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions notes: 1. b = binary, h = hex 2. the mt29f8g08fab device id code reflec ts the configuration of each 4gb section. table 8: device id and configuration codes options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value 1 notes byte 0 manufacturer id micron 001011002ch byte 1 device id mt29f2g08aab 2gb, x8, 3v 11011010dah mt29f2g16aab 2gb, x16, 3v 11001010cah mt29f4g08bab 4gb, x8, 3v 11011100dch mt29f4g16bab 4gb, x16, 3v 11001100cch mt29f8g08fab 8gb, x8, 3v 11011100dch 2 byte 2 byte value don?t care xxxxxxxxxxh byte 3 page size 2kb 0 1 01b spare area size (bytes) 64 0 1 01b block size (w/o spare) 128kb 0 1 01b organization x8 00b x16 11b reserved 00b byte value x8 0001010115h byte value x16 0101010155h 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 28 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions read status 70h these nand flash devices have an 8-bit status register that the software can read dur- ing device operation. on the x16 device, i/o[15:8] are ?0? when reading the status regis- ter. table 9 describes the status register. after a read status command, all read cycles will be from the status register until a new command is given. changes in the status register will be seen on i/o[7:0] as long as ce# and re# are low; it is not necessar y to start a new read cycle to see these changes. while monitoring the read status to determine when the t r (transfer from flash array to data register) is complete, the user must re -issue the read (00h) command to make the change from status to data. after the read command has been re-issued, pulsing the re# line will result in outputting data , starting from the initial column address. notes: 1. status register bit 5 is ?0? during the actual programming operation. if cache mode is used, this bit will be ?1? when al l internal operatio ns are complete. 2. status register bit 6 is ?1? wh en the cache is ready to accept new data. r/b# follows bit 6. see figure 19 on page 25, and figure 24 on page 30. figure 21: status register operation table 9: status register bit definition sr bit page program program page cache mode page read page read cache mode block erase definition 0 pass/fail pass/fail (n) ? ? pass/fail ?0? = successful program/erase ?1? = error in program/erase 1 ? pass/fail (n-1) ? ? ? ?0? = successful program/erase ?1? = error in program/erase 2? ? ? ? ? ?0? 3? ? ? ? ? ?0? 4? ? ? ? ? ?0? 5 ready/busy ready /busy 1 ready/busy ready /busy 1 ready/busy ?0? = busy ?1? = ready 6 ready/busy ready/busy cache 2 ready/busy ready/busy cache 2 ready/busy ?0? = busy ?1? = ready 7 write protect write protect write protect write protect write protect ?0? = protected ?1? = not protected [15:8] ? ? ? ? ? ?0? 70h ce# cle we# re# i/ox status output t rea t clr t clea 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 29 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions program operations program page 80h?10h micron nand flash devices are inherently page-programmed devices. within a block, the pages must be programmed consecutively from the least significant bit (lsb) page of the block to most significant bit (msb) pa ges of the block. random page address pro- gramming is prohibited. micron nand flash devices also support pa rtial-page programming operations. this means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of eight programming oper- ations are allowed before an erase is required. serial data input 80h page program operations require loading the serial data input (80h) command into the command register, followed by five address cycles, then the data. serial data is loaded on consecutive we# cycles starti ng at the given address. the program (10h) command is written after the data input is complete. the internal write state machine automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. write verifi cation only detects ?1s? that are not suc- cessfully written to ?0s.? r/b# goes low for the duration of array programming time, t prog. the read status register (70h) command and the reset (ffh) command are the only commands valid during the programming operation. bit 6 of th e status register will reflect the state of r/b#. when the device reaches re ady, read bit 0 of the status register to determine if the program operation passed or failed. (see figu re 22.) the command register stays in read status register mode until another valid command is written to it. random data input 85h after the initial data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input com- mand can be used any number of times in the same page prior to issuing the page write (10h) command. see figure 23 for the proper command sequence. figure 22: program and read status operation figure 23: random data input i/ox 80h address (5 cycles) 10h 70h r/b# t prog status i/o 0 = 0 program successful i/o 0 = 1 program error d in i/ox 80h address (5 cycles) 85h address (2 cycles) 10h 70h r/b# t prog d in d in status 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 30 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions program page cache mode 80h?15h cache programming is actually a buffered programming mode of the standard page program command. programming is started by loading the serial data input (80h) command to the command register, followed by five cycles of address, and a full or partial page of data. the data is initially copied into the cache register, and the cache write (15h) command is then latched to th e command register. data is transferred from the cache register to the data register on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data register and r/b# returns to high, memory array programming begins. when r/b# returns to high, new data can be written to the cache register by issuing another cache program command sequence. th e time that r/b# stays low will be controlled by the actual programming time. the first time through equals the time it takes to transfer the cache register contents to the data register. on the second and sub- sequent programming passes, transfer from the ca che register to the data register is held off until current data register content has been programmed into the array. bit 6 (cache r/b#) of the status register can be read by issuing the read status (70h) command to determine when the cache register is ready to accept new data. the r/b# pin always follows bit 6. bit 5 (r/b#) of the status register can be polled to determine when the actual program- ming of the array is complete for the current programming cycle. if just the r/b# pin is used to determine programming completion, the last page of the program sequence must use the program page (10h) command instead of the cache program (15h) command. if the cache program (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when pr ogramming is complete. (see figure 24.) bit 0 of the status register returns the pass/f ail for the previous page when bit 6 of the status register is a ?1? (ready state). the pass/fail status of the current program opera- tion is returned with bit 0 of the status regist er when bit 5 of the status register is a ?1? (ready state). (see figure 24.) figure 24: program page cache mode example notes: 1. see note 3, table 19 on page 42. 2. check i/o[6:5] for in ternal ready/busy. check i/o[1:0] fo r pass fail. re# can stay low or pulse multiple times after a 70h command. t cbsy r/b# i/ox r/b# i/ox address & data input 80h 15h address & data input 80h 15h address & data input 80h 15h address & data input 80h 10h t cbsy t cbsy t lprog 1 t cbsy address & data input 80h 15h address & data input 80h 10h status 2 output 70h t prog status 2 output 70h a: without status reads. b: with status reads. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 31 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions internal data move an internal data move requires two comm and sequences. issue a read for internal data move (00h?35h) command first, then the internal data move (85h?10h) command. data moves are only supported within the die from which data is read. read for internal data move 00h?35h this read command is used in conjunction with the internal data move (85h? 10h) command. first, (00h) is written to the command register, then the internal source address is written (five cycles ). after the address is input, the read for internal data move (35h) command writes to the command register. this transfers a page from memory into the cache register. the written column addresses are ignored even though all five address cycles are required. the memory device is now ready to accept the internal data move (85h?10h) com- mand. please refer to the description of this command in the following section. internal data move 85h?10h after the read for internal data move command has been issued and r/b# goes high, the internal data move command can be written to the command register. this command transfers the data from the cach e register to the data register and program- ming of the new destination page begins . after the internal data move command and address sequence are written to the device, r/b# goes low while the internal con- trol logic automatically programs the new page. the read status command and bit 6 of the status register can be used instead of the r/b# line to determine when the write is complete. bit 0 of the status register indicates if the operation was successful. the random data input (85h) command can be used during the internal data move command sequence to modify a word or multiple words of the original data. first, data is copied into the cache register using the 00h?35h command sequence, then the random data input (85h) command is wr itten along with the address of the data to be modified next. new data is input on the external data pins. this copies the new data into the cache register. when 10h is written to the command register, the original data plus the modified data is transferred to the data register, and progra mming of the new page is started. the ran- dom data input command can be issued as many times as necessary before starting the programming sequence with 10h. (see figures 25 and 26 on page 32.) because the internal data move operation does not utilize external memory, ecc cannot be used to check for errors before programming the data to a new page. this can lead to a data error if the source page cont ains a bit error due to charge loss or charge gain. in the case that multiple internal data move operations are performed, these bit errors may accumulate without correction. for this reason, it is highly recommended that systems utilizing the internal data move operation use a robust ecc scheme that can correct two or more bits per sector. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 32 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions figure 25: internal data move figure 26: internal data move with random data input i/ox 00h address (5 cycles) 35h 85h address (5 cycles) 10h 70h r/b# t prog t r status i/ox 00h address (5 cycles) 35h 85h address (5 cycles) data data 85h address (2 cycles) unlimited number of repetitions. 10h 70h status r/b# t prog t r 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 33 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions block erase operation block erase 60h ? d0h erasing occurs at the block level. for ex ample, the mt29f2g08xxb device has 2,048 erase blocks organized as 64 2,112-byte (2,048 + 64 bytes) pages per block. each block is 132k bytes (128k + 4k bytes). the block erase command operates on one block at a time. (see figure 27.) three cycles of addresses a[28:18] are requir ed for the x8 device, and three cycles of addresses [27:17] are required for the x16 device. although addresses a[17:12] (x8) and a[16:11] (x16) are loaded, they are a ?don?t care? and are ignored for block erase operations. (see figures 5 and 6 on page 10 for addressing details.) the actual command sequence is a two-st ep process. the erase setup (60h) com- mand is first written to the command register. then three cycles of addresses are written to the device. next, the erase confirm (d0h) command is written to the command register. at the rising edge of we#, r/b# go es low and the internal write state machine automatically controls the timing and erase- verify operations. r/b# stays low for the entire t bers erase time. the read status register command can be used to check the status of the erase operation. when bit 6 = ?1? the erase operat ion is complete. bit 0 indicates a pass/fail condition where ?0? = pass. (see figure 27, and table 9 on page 28.) figure 27: block erase operation re# ce# ale cle i/ox 60h address input (3 cycles) status d0h 70h r/b# we# t bers don?t care i/o 0 = 0 erase successful i/o 0 = 1 erase error 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 34 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions reset operation reset ffh the reset command is used to put the memory device into a known condition and to abort a command sequence in progress. random read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memo ry location being programmed or the block being erased are no longer valid. the data may be partially erased or programmed, and is invalid. the command register is cleared and is ready for the next command. the status register contains the value e0h when wp# is high; otherwise it is written with a 60h value. r/b# goes low for t rst after the reset command is written to the command register. (see figure 28 and table 10.) figure 28: reset operation table 10: status register contents after reset operation condition status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex wp# high ready 11100000e0h wp# low read and write protected 0110000060h cle ce# we# r/b# i/ox t rst t wb ff reset command 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 35 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions write protect operation the write protect feature protects the device against inadvertent program and erase operations. all program and erase oper ations are disabled when wp# is low. for write protect timing detail s, see figures 29 through 32. figure 29: erase enable figure 30: erase disable figure 31: program enable t ww 60h d0h we# i/ox wp# r/b# t ww 60h d0h we# i/ox wp# r/b# t ww 80h 10h we# i/ox wp# r/b# 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 36 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory command definitions figure 32: program disable t ww 80h 10h we# i/ox wp# r/b# 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 37 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory error management error management micron nand devices are specified to have a minimum of 2,008 (n vb ) valid blocks out of every 2,048 total available blocks. this means the device s may have blocks that are invalid when they are shipped. an invalid block is one that contains one or more bad bits. additional bad blocks may develop with use. however, the total number of avail- able blocks will not fall below n vb during the endurance life of the product. although nand memory devices may contain bad blocks, they can be used quite reli- ably in systems that provide bad-block mapping, replacement, and error correction algorithms. this type of software environment ensures data integrity. internal circuitry isolates ea ch block from other blocks, so the presence of a bad block does not affect the operation of the rest of the flash device. the first block in each micron nand device is guaranteed to be free of defects when shipped from the factory (up to 1,000 program/ erase cycles). this provides a reliable location for storing boot code and critical boot information. before nand devices are shipped from micron, they are erased. the factory identifies invalid blocks before shipping by programmin g data other than ffh (x8) or ffffh (x16) into the first spare location (column addr ess 2,048 for x8 devices, or 1,024 for x16 devices) of the first 2 pages of each bad block. system software should check the first spare address on the first 2 pages of each block prior to performing any erase or programmi ng operations on the flash device. a bad block table can then be created, allowing system software to map around these areas. factory testing is performed under worst-case conditions. because blocks marked ?bad? may be marginal, it may not be possible to recover this information if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over th e life of the flash device, certain precautions must be taken, such as: always check status after a write, erase, or data move operation. use some type of error detection and correc tion algorithm to reco ver from single-bit errors. use a bad-block replacement algorithm. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 38 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory electrical characteristics electrical characteristics stresses greater than those listed under ?absolute maximum ratings? may cause per- manent damage to the device. this is a stress rating only , and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this specification is not guaranteed . exposure to absolute maximum rating con- ditions for extended periods may affect reliability. table 11: absolute maximum ratings by device device symbol min max unit mt29fxgxxxax v in supply voltage on any pin relative to vss ?0.6 +4.6 v mt29fxgxxxax v cc storage temperature t stg ?6 5 +150 c short circuit output current, i/os 5ma table 12: recommended operating conditions parameter/condition symbol min typ max unit operating temperature commercial t a0?+70 o c extended t a?40?+85 o c v cc supply voltage vcc 2.7 3.3 3.6 v supply voltage vss 0 0 0 v 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 39 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory electrical characteristics v cc power cycling micron nand flash devices are designed to prevent data corruption during power tran- sitions. v cc is internally monitored. when v cc goes below 1.1v, program and erase functions are disabled. wp# provides additi onal hardware protection. wp# should be kept at v il during power cycling. when v cc reaches 1.1v, a minimum of 10s should be allowed for the flash to initialize before executing any commands. (see figure 16 on page 21.) note: the pre function is not suppo rted on extended-temperature devices. table 13: dc and operating characteristics parameter conditions symbol min typ max unit sequential read current t cycle = 30ns, ce# = v il , i out = 0ma icc1 ? 15 30 ma program current ?i cc 2 ? 15 30 ma erase current ?i cc 3 ? 15 30 ma standby current (ttl) ce# = v ih , pre = wp# = 0v/v cc i sb 1? ? 1 ma standby current (cmos) mt29f2gxxaab ce# = v cc - 0.2v, pre = wp# = 0v/v cc i sb 2 ? 10 50 a standby current (cmos) mt29f4gxxbab mt29f8g08fab ce# = v cc - 0.2v, pre = wp# = 0v/v cc i sb 2 ? 20 100 a input leakage current v in = 0v to v cc i li ? ? 10 a output leakage current v out = 0v to v cc i lo ? ? 10 a input high voltage i/o [7?0], i/o [15?0] ce#, cle, ale, we#, re#, wp#, pre, r/b# v ih 0.8 x vcc ? v cc + 0.3 v input low voltage (all inputs) ?v il -0.3 ? 0.8 v output high voltage i oh = -400a v oh 2.4 ? ? v output low voltage i ol = 2.1ma v ol ??0.4v output low current (r/b#) v ol = 0.4v i ol (r/b#) 8 10 ? ma 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 40 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory electrical characteristics notes: 1. invalid blocks are blocks that contain on e or more bad bits. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; however, the total number of available blocks will not drop be low nvb during the endurance life of the device. do not erase or program bloc ks marked invalid by the factory. 2. block 00h (the first block) is guaranteed to be valid and does not require error correction up to 1,000 program/erase cycles. notes: 1. these parameters are verified in device characterization and are not 100% tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. notes: 1. verified in device characterization; not 100% tested. table 14: valid blocks parameter symbol device min max unit notes valid block number n vb mt29f2gxxaab 2,008 2,048 blocks 1, 2 mt29f4gxxbab 4,016 4,096 mt29f8g08fab 8,032 8,192 table 15: capacitance description symbol device max unit notes input capacitance c in mt29f2gxxaab 10 pf 1, 2 mt29f4gxxbab 20 mt29f8g08fab 40 input/output capacitance (i/o) c io mt29f2gxxaab 10 pf 1, 2 mt29f4gxxbab 20 mt29f8g08fab 40 table 16: test conditions parameter value notes input puls e levels?mt29fxgxxxab 0.0v to 3.3v input rise and fall times 5ns input and output timing levels v cc /2 output load mt29fxgxxxab (v cc = 3.0v 10%) 1 ttl gate and cl = 50pf mt29fxgxxxab (v cc = 3.3v 10%) 1 ttl gate and cl = 100pf 1 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 41 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory electrical characteristics notes: 1. timing for t adl begins in the address cy cle, on the final rising edge of we#, and ends with the first rising edge of we# for data input. 2. for page read cache mode and program page cache mode operations, the x16 ac characteristics apply for both x16 and x8 devices. table 17: ac characteristics?comm and, data, and address input parameter symbol x16 x8 unit notes min max min max ale to data start t adl 100 ? 100 ? ns 1 ale hold time t alh 10 ? 5 ? ns 2 ale setup time t als 25 ? 10 ? ns 2 ce# hold time t ch 10 ? 5 ? ns 2 cle hold time t clh 10 ? 5 ? ns 2 cle setup time t cls 25 ? 10 ? ns 2 ce# setup time t cs 35 ? 15 ? ns 2 data hold time t dh 10 ? 5 ? ns 2 data setup time t ds 20 ? 10 ? ns 2 write cycle time t wc 45 ? 30 ? ns 2 we# pulse width high t wh 15 ? 10 ? ns 2 we# pulse width t wp 25 ? 15 ? ns 2 wp# setup time t ww 30 ? 30 ? ns 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 42 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory electrical characteristics notes: 1. for page read cache mode and program page cache mode operations, the x16 ac characteristics apply for both x16 and x8 devices. 2. transition is measured 200mv from steady- state voltage with load. this parameter is sampled and not 100% tested. 3. if reset (ffh) command is loaded at ready state, the device goes busy for maximum 5s. 4. do not issue a ne w command during t wb, even if r/b# is ready. 5. the pre function is not supported on extended-temperature devices. notes: 1. eight total to the same page. 2. t cbsy max time depends on timing between in ternal program completion and data in. 3. t lprog = t prog (last page) + t prog (last ? 1 page) ? cmd load time (last page) ? addr load time (last page) ? data load time (last page). table 18: ac characteristics?normal operation parameter symbol x16 x8 unit notes min max min max ale to re# delay t ar 10 ? 10 ns ce# access time t cea ?45?23ns1 ce# high to output high-z t chz ?20?20ns2 cle access time t clea ?45?28ns1 cle to re# delay t clr 10 ? 10 ? ns cache busy in page read cache mode (first 31h) t dcbsyr1 ?3?3s cache busy in page read cache mode (next 31h and 3fh) t dcbsyr2 t dcbsyr1 25 t dcbsyr1 25 s ouput high-z to re# low t ir 0?0?ns1 data output hold time t oh 15 ? 15 ? ns data transfer from flash array to data register t r ?25?25s read cycle time t rc 50 ? 30 ? ns 1 re# access time t rea ?30?18ns1 re# high hold time t reh 15 ? 10 ? ns 1 re# high to output high-z t rhz ?30?30ns2 re# pulse width t rp 25 ? 15 ? ns 1 data transfer from flash array to data register at power-up with pre enabled @ 3.3v vcc t rpre ?25?25s ready to re# low t rr 20 ? 20 ? ns reset time (read/program/erase) t rst ? 5/10/500 ? 5/10/500 s 3 we# high to busy t wb ?100?100ns3, 4 we# high to re# low t whr 60 ? 60 ? ns table 19: program/erase characteristics parameter symbol typ max unit notes number of partial page programs nop ?8cycle1 block erase time t bers 23ms busy time for cache program t cbsy 3 700 s 2 last page program time t lprog ???3 page program time t prog 300 700 s 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 43 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams timing diagrams figure 33: command latch cycle note: x16: i/o[15:8] must be set to ?0. figure 34: address latch cycle note: x16: i/o [15:8] must be set to ?0.? we# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls don?t care we# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 don?t care undefined t wc 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 44 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 35: input data latch notes: 1. d in final = 2,111 (x8) or 1,055 (x16). figure 36: serial access cycle after read we# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in 1 d in final 1 don?t care t wc d in 0 ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea don?t care t rhz t chz t rhz t oh r/b# t oh d out d out d out 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 45 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 37: status read cycle figure 38: page read re# ce# we# cle i/ox t rhz t wp t whr t clea t clr t ch t cls t cs t clh t dh t oh t rp t chz t ds t rea t oh t ir 70h status output don?t care t cea d out n d out n + 1 d out m we# ce# ale cle re# r/b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz don?t care col add 1 col add 2 row add 1 row add 2 row add 3 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 46 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 39: read operation with ce# ?don?t care? figure 40: random data read re# ce# t rea t cea re# ce# ale cle i/ox i/ox out r/b# we# data output t r don?t care address (5 cycles) 00h 30h we# ce# ale cle re# r/b# i/ox busy col add1 col add2 row add1 row add2 row add3 00h t r t wb t ar t rr don?t care t rc d out m d out m + 1 col add1 col add2 05h e0h t rea t clr t clea d out n d out n + 1 30h t whr 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 47 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 41: page read cache mode timing diagram, part 1 of 2 t wc we# ce# ale cle re# r/b# i/ox column address 0 1 d out page address m page address m + 1 t cea t ds t clh t cls t cs t ch t dh don?t care t rr t wb t r t dcbsyr1 t dcbsyr2 column address 0 continued to 1 of next page t rc t rea 30h d out 0 d out 0 d out 1 column address 00h page address m 31h 31h col add 1 col add 2 row add 1 row add 2 row add 3 00h 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 48 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 42: page read cache mode timing diagram, part 2 of 2 we# ce# ale cle re# r/b# i/ox 1 page address m + 1 don?t care page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t clh t ch t rea t cea t ds t dh t rr t dcbsyr2 t dcbsyr2 t dcbsyr2 t wb column address 0 d out 0 d out 1 d out 31h d out 0 d out 3fh d out 1 d out 0 d out d out 1 t cls t cs t rc d out 31h 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 49 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 43: page read cache mode timing without r/b#, part 1 of 2 t wc we# ce# ale cle re# i/ox 30h 70h status d out 0 column address 0 1 d out 0 d out 1 d out column address 00h page address m page address m + 1 page address m t cea t ds t clh t cls t cs t ch t dh don?t care 31h 31h column address 0 70h status i/o 6 = 0, cache busy = 1, cache ready i/o 5 = 0, busy = 1, ready continued to 1 of next page col add 1 col add 2 row add 1 row add 2 row add 3 00h 00h 00h t rc t rea 70h status i/o 6 = 0, cache busy = 1, cache ready 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 50 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 44: page read cache mode timing without r/b#, part 2 of 2 we# ce# ale cle re# i/ox 1 page address m + 1 don?t care page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t rea t cea t ds t dh column address 0 d out 0 d out 1 d out 31h d out 0 d out 3fh d out 1 d ou t d out 1 d out 0 t rc d out 31h 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 00h 00h 00h t clh t ch t cls t cs 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 51 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 45: read id operation figure 46: program operation with ce# ?don?t care? device id 1 don't care w e# ce# ale cle re# i/ox address, 1 cycle 90h 00h manufacturer id 1 byte 2 byte 0 byte 1 byte 3 1 t ar t rea t whr cle ce# we# ale i/ox address (5 cycles) data input 10h we# ce# t wp t ch t cs don?t care data input 80h 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 52 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 47: program page operation figure 48: program page operation with random data input we# ce# ale cle re# r/b# i/ox t wc t adl serial data input command x8 device: m = 2,111 byte x16 device: m = 1,055 byte program command read status command 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog t wb don?t care we# ce# ale cle re# r/b# i/ox t wc serial data input command serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in n+1 t adl t adl random data input command column address program command read status command serial input 85h t prog t wb don?t care col add 1 col add 2 d in n d in n+1 70h status 10h 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 53 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 49: internal data move figure 50: program page cache mode note: program page cache mode operations must not cross die address boundaries. we# ce# ale cle re# r/b# i/ox t wb t r t prog t wb busy busy read status command t wc internal data move don?t care t adl col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h 35h col add 2 row add 1 row add 2 row add 3 col add 1 85h data 1 we# ce# ale cle re# r/b# i/ox 15h t cbsy t wb t wb t prog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page - 1 last page serial data input serial input program program t wc don?t care 80h t adl row add 3 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 54 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 51: program page cache mode ending on 15h we# ce# ale cle re# i/ox 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page -1 serial data input serial input program program t wc don?t care 80h poll status until: i/o6 = 1, ready to ensure program success, last 2pages: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page -1 program successful t adl 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 55 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory timing diagrams figure 52: block erase operation notes: 1. see table 8 on page 27 for actual values. figure 53: reset operation w e# ce# ale cle re# r/b# i/ox erase setup command erase command read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb don?t care cle ce# we# r/b# i/ox t rst t wb ff reset command ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trad emarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 2, 4, and 8gb x8/x16 multiplexed nand flash memory package information 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 56 ?2004 micron technology, inc. all rights reserved. package information all dimensions in millimeters; min/max, or typical, as noted. figure 54: package dimensions note: for design guidelines using the 8gb device, see technical note 2909, at: www.micron.com/products/ nand/massstorage/technote 1.20 max 0.15 +0.03 -0.02 0.20 0.05 see detail a 0.50 typ 18.40 0.08 20.00 0.25 12.00 0.08 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 pin #1 index plated lead finish: 90% sn, 10% pb or 100%sn plastic package material: novolac epoxy package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. 09005aef818a56a7 pdf/ 09005aef81590bdd source micron technology, inc., reserves the right to change products or specifications without notice. 2gb_nand_m29b__2.fm - rev. c 5/05 en 57 ?2004 micron technology, inc. all rights reserved. 2, 4, and 8gb x8/x16 multiplexed nand flash memory revision history revision history rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/05 added write protect. updated standby current descriptions. rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/05 updated package drawing. initial release, rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/05 |
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